Re: The VLIW bundle output questions

Ling-hua Tseng wrote: > > For example: > ===[top] > mov .risc0 r1, #25 \\ > ldw .risc0 r2, [fp, #30] \\ > addub .mac0 d0, d4, d3 \\ > subub .mac1 d11, d7, d4 > add .risc0 r3, r1, r5 > ===[end]==

The VLIW bundle output questions

I'm porting gcc to a uni-core architecture (i.e., only one core). There are 10 function units: (1) 2 RISCs: the 2 RISC have the same capability and they can do load/store, full-word arithmetic/logic operations, register move, ... (2) 4 DSPs ( 2 MAC, 1 BSU, and 1 VFU):