Jon,
How is the latency of instructions that have side effects modeled in the DFA
scheduler. For example, define_insn_reservation only has one latency value,
yet instructions such as loads with post increment addressing have two
outputs, possibly with different latencies. Do both outputs get the sa
Hi,
How is the latency of instructions that have side effects modeled in the DFA
scheduler. For example, define_insn_reservation only has one latency value,
yet instructions such as loads with post increment addressing have two
outputs, possibly with different latencies. Do both outputs get the sa
