On Fri, Jun 21, 2013 at 9:22 AM, Hendrik Greving
wrote:
> A question regarding regalloc (probably greg?)
>
> I understand that matching constraints can constrain allocation to
> re-use registers, e.g. for an 'add' actually has 2 instruction
> operands (instead of 3). This is documented well. But w
A question regarding regalloc (probably greg?)
I understand that matching constraints can constrain allocation to
re-use registers, e.g. for an 'add' actually has 2 instruction
operands (instead of 3). This is documented well. But what about if I
do not necessarily constrain the output template, e
Bingfeng Mei wrote:
I found if I define a new register class that covers both GR_REGS and PR_REGS, the issue can be solved. New IRA spill the predicate register to general regsister first instead of memory. Is this right approach?
#define IRA_COVER_CLASSES \
{ \
GRP
Bingfeng Mei wrote:
Hello,
I recently ported our GCC to new IRA by following mainline development. The
only interface I added is IRA_COVER_CLASSES. Our architecture has predicate
register file. When predicate register has to be spilled, the new IRA produces
inferior code to the old register a
, BXBC_REGS, LIM_REG_CLASSES \
}
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On
> Behalf Of Bingfeng Mei
> Sent: 02 January 2009 11:50
> To: gcc@gcc.gnu.org
> Cc: Vladimir Makarov
> Subject: [IRA] New register allocator que
Hello,
I recently ported our GCC to new IRA by following mainline development. The
only interface I added is IRA_COVER_CLASSES. Our architecture has predicate
register file. When predicate register has to be spilled, the new IRA produces
inferior code to the old register allocator. The old all
