On 09/09/2009 09:59 AM, Alex Turjan wrote:
1.What do you think about this implementation? using define_insn_and_split
If this port uses BITS_PER_WORD=16, then the lower-subreg pass may
be able to give you better register allocation by disconnecting the
low and high parts of the 32-bit value.
I
Hi Michael,
> My assumption would be these two split loads of HImode are
> generated by your backend from a given SImode MEM.
Indeed your asumption is right. Bellow I have a mulsi3 expand in which I
generate insns of mode HI. operands[1] gets spilled: in the produced BB as a
single SI store wh
Hi,
On Tue, 8 Sep 2009, Alex Turjan wrote:
> (insn 374 47 52 2 test.c:107 (set (mem/c:SI (plus:PSI (reg/f:PSI 55 ptr15)
> (const_int 96 [0x60])) [19 fac_iter+0 S4 A32])
> (reg/v:SI 16 r16 [orig:161 step109 ] [161])) 48
> {si_indexed_store_incl_ra} (nil))
An SI store to
Alex Turjan wrote:
> Dear all,
> Im writing to you regarding the dead store elimination (dse) which runs after
> register allocation. Apparently dse removes wrongly the following store
> (present in bb2):
>
> (insn 374 47 52 2 test.c:107 (set (mem/c:SI (plus:PSI (reg/f:PSI 55 ptr15)
>
