Yes. You are right. I fixed the problem.
I checked the macro in INTERNAL docment, and I copied the mips
definition of PROMOTE_MODE:
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
{
daniel tian writes:
> But the question is how I make the gcc know to extend every smaller
> mode to SImode. Now I check the MIPS port, maybe I can find some clue.
Maybe PROMOTE_MODE.
Ian
Thank you for your advice. Compared RICE (my processor name) RTL and
MIPS RTL, I found the problem. Because of the subreg operations which
I missed to add support in my RTL. I noticed the mips rtl code which
will convert the QImode and HI mode to SImode operations. Like the
following:
(insn 28 26
daniel tian writes:
> I am porting gcc to a 32bit RISC chip, and I met a logical
> error with 16bit arithmetic operations in generating assemble code.
> the error is between two 16bit data movement(unsigned short).
> While like A = B, A, and B are all unsigned short type. B is a
> result
