Joseph S. Myers wrote:
On Fri, 4 Apr 2008, Michael Eager wrote:
Xilinx has a PowerPC 405 processor with an attached
single precision floating point processor. I have a
patch which supports this FP unit, but want to clean
it up a bit before submitting it.
What do you propose as the function c
On Fri, 4 Apr 2008, Michael Eager wrote:
> Xilinx has a PowerPC 405 processor with an attached
> single precision floating point processor. I have a
> patch which supports this FP unit, but want to clean
> it up a bit before submitting it.
What do you propose as the function call and return ABI
Daniel Jacobowitz wrote:
On Sun, Apr 06, 2008 at 10:25:38AM -0700, Michael Eager wrote:
For an instruction supported on all variants (both BookE and E500)
with a double precision FPU.
I think you have your terminology switched. E500 is (very
approximately) an implementation of Book E; the FPR
On Sun, Apr 06, 2008 at 10:25:38AM -0700, Michael Eager wrote:
> For an instruction supported on all variants (both BookE and E500)
> with a double precision FPU.
I think you have your terminology switched. E500 is (very
approximately) an implementation of Book E; the FPR-based FPU is
usually cal
You need to negotiate this with the E500 developers who created
this set of options.
David
David Edelsohn wrote:
I would prefer feature-based.
TARGET_HARD_FLOAT represents the presence of FPUs.
TARGET_FPRS represents the presence of FP register set because
one variant used GPRs for FP operations.
E500 then added another variant with double-precision F
I would prefer feature-based.
TARGET_HARD_FLOAT represents the presence of FPUs.
TARGET_FPRS represents the presence of FP register set because
one variant used GPRs for FP operations.
E500 then added another variant with double-precision FP in the
GPRs.
