Re: Problem with memory alignment for 64 byte moves

Hi Ian Thanks for the response. All of those flags are set correctly, though it is still emitting loads and stores 4 byte aligned and not 8. I'm trying to get the compiler to combine two 4 byte loads in to a single 8 byte load as it is more efficient on this architecture, so I'm guessing because

Re: Problem with memory alignment for 64 byte moves

Neil Hickey writes: > I'm porting gcc to a new architecture and I'm allowing use of movdi > instructions as the processor allows 8 byte loads. The processor > however requires 8 byte loads and stores to be naturally aligned, yet > gcc seems to be emitting loads and stores that are 4 byte aligned.