On Wed, Jan 12, 2011 at 6:36 PM, Dave Korn wrote:
> On 12/01/2011 13:50, Jeff Law wrote:
>
>> On 01/12/11 01:45, Gidi Nave wrote:
>>
>>> One more question:
>>> GCC usually knows how to handle cases which need decomposition of
>>> expressions due to architecture limitations.
>>> In my case it didn'
On 12/01/2011 13:50, Jeff Law wrote:
> On 01/12/11 01:45, Gidi Nave wrote:
>
>> One more question:
>> GCC usually knows how to handle cases which need decomposition of
>> expressions due to architecture limitations.
>> In my case it didn't know.
>> How can I foreseen additional such cases, in ord
On Wed, Jan 12, 2011 at 3:50 PM, Jeff Law wrote:
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> On 01/12/11 01:45, Gidi Nave wrote:
>
>>
>> One more question:
>> GCC usually knows how to handle cases which need decomposition of
>> expressions due to architecture limitations.
>> In my case i
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On 01/12/11 01:45, Gidi Nave wrote:
>
> One more question:
> GCC usually knows how to handle cases which need decomposition of
> expressions due to architecture limitations.
> In my case it didn't know.
> How can I foreseen additional such cases, in
On Wed, Jan 12, 2011 at 8:27 AM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor wrote:
>>> Gidi Nave writes:
>>>
On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
> So why doesn't d1 = d1 + -96 match the last instruction
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor wrote:
>> Gidi Nave writes:
>>
>>> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>>>
So why doesn't d1 = d1 + -96 match the last instruction there?
>>> because it's: add d,d unsigned
>>> we don't have
On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>>
>>> So why doesn't d1 = d1 + -96 match the last instruction there?
>>>
>> because it's: add d,d unsigned
>> we don't have: add d,d signed
>>
>> and in
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>
>> So why doesn't d1 = d1 + -96 match the last instruction there?
>>
> because it's:add d,d unsigned
> we don't have: add d,d signed
>
> and in this case we need: d = r + (-96)
(Please don't top-post on this mai
because it's:add d,d unsigned
we don't have: add d,d signed
and in this case we need: d = r + (-96)
On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
>>> Gidi Nave writes:
>>>
I have a question
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
>> Gidi Nave writes:
>>
>>> I have a question regarding Plus reload situation I ran into in my
>>> port (which was taken from branch 4.6):
>>>
>>> I got the following insn: Set d1 (plus r1 -96).
>>> d1 and r1 are 2 r
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On 01/11/11 07:59, Gidi Nave wrote:
> Hi Ian,
>
> Relevant instruction supported:
>
> add r,r,r
> add r,r unsigned
> add r,r, signed
> add d,d,d
> add d,d unsigned
You're probably going to need a secondary reload to deal with this case
d = r + -const
oh,
I forgot:
move d,r(d = r)
On Tue, Jan 11, 2011 at 4:59 PM, Gidi Nave wrote:
> Hi Ian,
>
> Relevant instruction supported:
>
> add r,r,r
> add r,r unsigned
> add r,r, signed
> add d,d,d
> add d,d unsigned
>
> Thanks,
> Gal.
>
>
> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote
Hi Ian,
Relevant instruction supported:
add r,r,r
add r,r unsigned
add r,r, signed
add d,d,d
add d,d unsigned
Thanks,
Gal.
On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> I have a question regarding Plus reload situation I ran into in my
>> port (which was t
Gidi Nave writes:
> I have a question regarding Plus reload situation I ran into in my
> port (which was taken from branch 4.6):
>
> I got the following insn: Set d1 (plus r1 -96).
> d1 and r1 are 2 registers from different classes.
>
> The reload (which take place at: reload1.c , gen_reload(ou
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