On Thu, 27 Nov 2014, Mathias Roslund wrote:
> But isn't the result of an 8bit signed divide the same as the result of
> a 32bit signed divide when both operands are in the 8bit range? That is,
> shouldn't the optimizers be able to do the same for signed divide as
> well as shift operations?
At
> From: Joern Rennecke [mailto:joern.renne...@embecosm.com]
> Sent: Wednesday, November 26, 2014 6:13 PM
> To: Mathias Roslund
> Cc: GCC
> Subject: Re: Machine description and code generation
>
> On 26 November 2014 at 16:48, Mathias Roslund
> wrote:
> > Since the
On 26 November 2014 at 16:48, Mathias Roslund wrote:
> Since then I've added more instructions and gotten to the point where most
> stuff seems to be working. My current issue is that signed divide and all
> shift operations insists on sign/zero extending the operands, resulting in
> 32bit operati
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Jeff Law
> Sent: Wednesday, October 29, 2014 9:36 PM
> To: Mathias Roslund; gcc@gcc.gnu.org
> Subject: Re: Machine description and code generation
>
> On 10/29/14 07:40, Mathias Roslund wrote:
&
On 10/29/14 07:40, Mathias Roslund wrote:
Hello,
I'm considering attempting a 65816 target but decided it would be a good
idea to start with something simple in order to learn how GCC generate
code. So I created a minimal machine description with just two
instructions (plus the mandatory nop/jum
instruction that should be
moved but not?
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 14 May 2010 12:26
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
Hi Bengfeng,
Changing my instruction patterns
iharan Sandanagobalane [mailto:harihar...@picochip.com]
> Sent: 14 May 2010 12:26
> To: Bingfeng Mei
> Cc: gcc@gcc.gnu.org
> Subject: Re: Machine description question
>
> Hi Bengfeng,
> Changing my instruction patterns similar to the ones that you
> sent does
> get over t
ll porivate and not in mainline.
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 13 May 2010 10:17
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
The patterns for PUT/GET were
; Scalar Pu
BXM))
(unspec:BXBC [(reg:BXBC R_BX)] UNSPEC_BX)] < Important to avoid some
optimization.
Our port is still porivate and not in mainline.
Cheers,
Bingfeng
> -Original Message-
> From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
> Sent: 13 May 201
with same parameters would result in same value being produced. This
obviously is not the case for these communication instructions.
Do you have your code to do this using unspec in gcc mainline? Can you
point me to that, please?
Thanks
Hari
Bingfeng Mei wrote:
How do you define your imaginary register
g
> Subject: Re: Machine description question
>
> Thanks for your help BingFeng.
>
> I gave this a go and ended up with worse code (and worse
> memory usage)
> than before. I started with this experiment because of the compilers
> "All virtual regis
Thanks for your help BingFeng.
I gave this a go and ended up with worse code (and worse memory usage)
than before. I started with this experiment because of the compilers
"All virtual registers are assumed to be used and clobbered by
unspec_volatile" rule. The get/put instructions read/write t
Our architecture has the similar resource, and we use the first approach
by creating an imaginary register and dependency between these instructions,
i.e., every such instruction reads and write to the special register to
create artificial dependency. You may need to add a (unspec:..) as an
indepe
On Fri, Jun 05, 2009 at 05:11:06PM -0500, Graham Reitz wrote:
>
> Is there a machine description template in the gcc file source tree?
>
> If there is also template for the 'C header file of macro definitions'
> that would be good to know too.
>
> I did a file search for '.md' and there are to
On 6/5/09, Graham Reitz wrote:
> I have been working through sections 16 & 17 of the gccint.info
> document and also read through Hans' 'Porting GCC for Dunces'.
There is also "Incremental Machine Descriptions for GCC"
http://www.cse.iitb.ac.in/~uday/soft-copies/incrementalMD.pdf
which describes
Graham Reitz wrote:
Is there a machine description template in the gcc file source tree?
If there is also template for the 'C header file of macro definitions'
that would be good to know too.
I did a file search for '.md' and there are tons of examples.
Although, I was curious if there was
Excellent! Thanks Ramana and Michael.
I have been working through sections 16 & 17 of the gccint.info
document and also read through Hans' 'Porting GCC for Dunces'.
He sure wasn't kidding mentioning you would need to read them several
times.
graham
On Jun 5, 2009, at 5:46 PM, Michael H
I've found the MMIX port to be a good place to start. It's a bit old
but the archtecture is nice and simple and the implementation nice and
brief. Watch out though as it is a pure 64 bit machine - you'll need
to think SI every time you see DI.
The trick past there is to compare the significant f
On Fri, Jun 5, 2009 at 11:11 PM, Graham Reitz wrote:
>
> Is there a machine description template in the gcc file source tree?
There is no template as such but you could look at existing ports for
the basic templates. Google should give you results for previous
questions on this list regarding new
Jean Christophe Beyler writes:
> For the moment, no change, the expansion code is actually not used in
> this case because GCC only presents me with the load from a global
> during or after reload. Therefore, it's already done and he doesn't
> seem to want to change his ways. I haven't played wit
I've actually done that. I defined the expansion like this:
/* If we can create pseudos, the first operand is a register but the
second is memory */
if (
(
can_create_pseudo_p () &&
register_operand (operands[0], DImode)
&& memory_operand (operands[1], DImode)))
Jean Christophe Beyler writes:
> I've been working on the Machine description of my target and was
> wondering if you could help me out here.
>
> I've been trying to force GCC out of it's habit of generating this code :
> (insn 28 8 10 2 glob.c:13 (set (reg:DI 9 r9)
> (mem/s:DI (symbol_re
Ok, I understand now. Thank you very much for your explanations,
Jean Christophe Beyler
On Sat, Feb 7, 2009 at 5:13 PM, Michael Meissner
wrote:
> On Sat, Feb 07, 2009 at 03:54:51PM -0500, Jean Christophe Beyler wrote:
>> Dear all,
>>
>> I have a question about the way the machine description wor
On Sat, Feb 07, 2009 at 03:54:51PM -0500, Jean Christophe Beyler wrote:
> Dear all,
>
> I have a question about the way the machine description works and how
> it affects the different passes of the compiler. I was reading the GNU
> Compiler Collection Internals and I found this part (in section
>
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