Re: Instruction scheduling for the R5900's 2 integer pipelines

2016-02-05 Thread Jeff Law
On 02/05/2016 05:35 AM, Woon yung Liu wrote: The current (GCC 5.3.0) MIPS divmod4 pattern emits an expand that allocates a temporary register (hi+lo) and emits other instructions, depending if whether the target is a 32-bit or 64-bit MIPS target. However, it uses gen_rtx_REG to allocate the hi+

Re: Instruction scheduling for the R5900's 2 integer pipelines

2016-01-19 Thread Jeff Law
On 01/19/2016 09:22 AM, Woon yung Liu wrote: Right now, I do have an old homebrew GCC v3.2.2 port to study as well, but I didn't follow everything from it because I didn't want to risk including obsolete constructs. Thanks for the information on the old Cygnus port. I'll try to scrape together

Re: Instruction scheduling for the R5900's 2 integer pipelines

2016-01-19 Thread Jeff Law
On 01/19/2016 05:04 AM, Woon yung Liu wrote: Hi, I'm am trying to complete support for the MIPS R5900, by adding support for its second interger multiplication/division pipe. GCC currently supports only the first one.My target at this moment is the public GCC v5.3.0 release. To get the 2