> There are some other quirks with the MicroBlaze architecture.
> The cmp/cmpu instructions only take a register. Other instructions
> which can be used for equality or signed comparisons (xor or sub)
> can take an immediate operand. I'll see how they can be added.
You can probably convince comb
Paolo Bonzini wrote:
On 12/21/2009 08:10 PM, Richard Henderson wrote:
(define_insn_and_split "*cmp"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))]
""
"cmp %0,%1
On 12/21/2009 08:10 PM, Richard Henderson wrote:
(define_insn_and_split "*cmp"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))]
""
"cmp %0,%1,%2\;andi $0,$0,1"
On 12/18/2009 03:18 PM, Michael Eager wrote:
MicroBlaze has a bit unusual compare and branch architecture.
There are no condition flags; comparison results are stored in
a result register.
This like Alpha or MIPS then.
There's one branch instruction, which compares a register
with zero and br
On 12/19/2009 01:07 AM, Joern Rennecke wrote:
Quoting Michael Eager :
Hi --
I'm working on creating the cstore and cbranch templates
for the Xilinx MicroBlaze processor.
In theory cstore / cbranch should be the future, but the last time I tried
to use them, they didn't quite work right yet,
Joern Rennecke wrote:
Quoting Michael Eager :
Hi --
I'm working on creating the cstore and cbranch templates
for the Xilinx MicroBlaze processor.
In theory cstore / cbranch should be the future, but the last time I tried
to use them, they didn't quite work right yet, particularily if you hav
Quoting Michael Eager :
Hi --
I'm working on creating the cstore and cbranch templates
for the Xilinx MicroBlaze processor.
In theory cstore / cbranch should be the future, but the last time I tried
to use them, they didn't quite work right yet, particularily if you have
an incomplete compari
