Re: [RISC-V] vector segment load/store width as a riscv_tune_param

On Wed, Mar 26, 2025 at 1:44 AM Robin Dapp wrote: > > You won't see failures in the testsuite. The failures only show-up when I > > attempt to impose huge costs on NF above threshold. A quick & dirty way > to > > expose the bug is apply the appended patch, then observe that you get > output > > f

Re: [RISC-V] vector segment load/store width as a riscv_tune_param

You won't see failures in the testsuite. The failures only show-up when I attempt to impose huge costs on NF above threshold. A quick & dirty way to expose the bug is apply the appended patch, then observe that you get output from this only for mask_struct_store-*.c and not for mask_struct_load-*.

Re: [RISC-V] vector segment load/store width as a riscv_tune_param

On Tue, Mar 25, 2025 at 2:47 AM Robin Dapp wrote: > > A year ago, Robin added minimal and not-yet-tunable > > common_vector_cost::segment_permute_[2-8] > > But it is tunable, just not a param? :) I meant "param" generically, not necessarily a command-line --param=thingy, though point taken! :)

Re: [RISC-V] vector segment load/store width as a riscv_tune_param

On 3/25/25 3:47 AM, Robin Dapp via Gcc wrote: I am revisiting an effort to make the number of lanes for vector segment load/store a tunable parameter. A year ago, Robin added minimal and not-yet-tunable common_vector_cost::segment_permute_[2-8] But it is tunable, just not a param? :)  We ha

Re: [RISC-V] vector segment load/store width as a riscv_tune_param

I am revisiting an effort to make the number of lanes for vector segment load/store a tunable parameter. A year ago, Robin added minimal and not-yet-tunable common_vector_cost::segment_permute_[2-8] But it is tunable, just not a param? :) We have our own cost structure in our downstream repo,