BLUE 3TOO writes:
> Ian, thanks a lot for the help. Is there any document
> about IRA (e.g. how the SIMD registers of a
> specific architecture is exposed to the allocation
> process)? or the only option is the read the code?
Vlad described IRA in a paper published in the 2007 GCC Summit
proc
.
> From: i...@google.com
> To: blue_3...@hotmail.com
> CC: gcc@gcc.gnu.org
> Subject: Re: vector register allocation
> Date: Fri, 25 Jun 2010 14:38:19 -0700
>
> BLUE 3TOO writes:
>
>> Can anybody explain how the register allocation is
BLUE 3TOO writes:
> Can anybody explain how the register allocation is handled in GCC?
> Is it done together with the general register allocation? or GCC
> has a separate phase to handle them separately?
There is no separate vector register allocator. All classes of
registers are al
