Hi,
I’ve spun an alternative version of RISC-V GCC which preserves RV64 ABI sign
extended canonicalisation for passed values but keeps values in SImode until
return.
https://github.com/michaeljclark/riscv-gcc/commits/riscv-gcc-7-mc
These are the changes:
- #undef PROMOTE_MODE
On 09/06/2017 11:17 AM, Richard Henderson wrote:
> On 09/06/2017 09:53 AM, Jeff Law wrote:
>>> I think the easiest solution to this is for combine to notice when IOR has
>>> operands with non-zero-bits that do not overlap, convert the operation to
>>> ADD.
>>> That allows the final two insns to fo
On 09/06/2017 10:17 AM, Richard Henderson wrote:
>> Yea. I'd also expect zero/nonzero bits tracking in combine to catch
>> this. Shouldn't the sign bit be known to be zero after the shift which
>> makes the extension redundant regardless of the SUBREG_PROMOTED flag?
> You're right, this should be
On 09/06/2017 09:53 AM, Jeff Law wrote:
>> I think the easiest solution to this is for combine to notice when IOR has
>> operands with non-zero-bits that do not overlap, convert the operation to
>> ADD.
>> That allows the final two insns to fold to "addw" and the compiler need do no
>> further ana
On 08/30/2017 02:43 AM, Michael Clark wrote:
> POINTERS_EXTEND_UNSIGNED -1 (which is true) is defined on some targets. I
> assume they sign-extend but the meaning has been overloaded.
Just for your edification, this is for e.g. ia64's "addp4" instruction and it
is not a normal extension. A 2-bit
On 09/06/2017 10:43 AM, Richard Henderson wrote:
> On 08/29/2017 05:36 PM, Michael Clark wrote:
>> We’re investigating an issue with redundant sign-extension instructions
>> being emitted with the riscv backend. Firstly I would like to state that
>> riscv is possibly a unique backend with respect
On 08/29/2017 05:36 PM, Michael Clark wrote:
> We’re investigating an issue with redundant sign-extension instructions being
> emitted with the riscv backend. Firstly I would like to state that riscv is
> possibly a unique backend with respect to its canonical sign-extended
> register form due t
> On 31 Aug 2017, at 2:12 PM, Michael Clark wrote:
>
>>
>> On 31 Aug 2017, at 7:20 AM, Matthew Fortune
>> wrote:
>>
>> Jeff Law writes:
>>> On 08/30/2017 06:52 AM, Richard Biener wrote:
On Wed, Aug 30, 2017 at 11:53 AM, Michael Clark
wrote:
>
>> On 30 Aug 2017, at 9:43
> On 31 Aug 2017, at 7:20 AM, Matthew Fortune
> wrote:
>
> Jeff Law writes:
>> On 08/30/2017 06:52 AM, Richard Biener wrote:
>>> On Wed, Aug 30, 2017 at 11:53 AM, Michael Clark
>>> wrote:
> On 30 Aug 2017, at 9:43 PM, Michael Clark wrote:
>
>>> diff --git a/gcc/simplify-r
Jeff Law writes:
> On 08/30/2017 06:52 AM, Richard Biener wrote:
> > On Wed, Aug 30, 2017 at 11:53 AM, Michael Clark
> > wrote:
> >>
> >>> On 30 Aug 2017, at 9:43 PM, Michael Clark wrote:
> >>>
> > diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
> > index ce632ae..25dd70f 100644
>
On 08/30/2017 12:34 AM, Michael Clark wrote:
>
>> On 30 Aug 2017, at 12:36 PM, Michael Clark wrote:
>>
>> Dear GCC folk,
>>
>>
>> # Issue Background
>>
>> We’re investigating an issue with redundant sign-extension instructions
>> being emitted with the riscv backend. Firstly I would like to stat
On 08/30/2017 06:52 AM, Richard Biener wrote:
> On Wed, Aug 30, 2017 at 11:53 AM, Michael Clark wrote:
>>
>>> On 30 Aug 2017, at 9:43 PM, Michael Clark wrote:
>>>
> diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
> index ce632ae..25dd70f 100644
> --- a/gcc/simplify-rtx.c
> ++
On Wed, Aug 30, 2017 at 11:53 AM, Michael Clark wrote:
>
>> On 30 Aug 2017, at 9:43 PM, Michael Clark wrote:
>>
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index ce632ae..25dd70f 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1503,6 +1503,10 @@ simp
> On 30 Aug 2017, at 9:43 PM, Michael Clark wrote:
>
>>> diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
>>> index ce632ae..25dd70f 100644
>>> --- a/gcc/simplify-rtx.c
>>> +++ b/gcc/simplify-rtx.c
>>> @@ -1503,6 +1503,10 @@ simplify_unary_operation_1 (enum rtx_code code,
>>> machine_mode m
> On 30 Aug 2017, at 9:14 PM, Richard Biener wrote:
>
> On Wed, Aug 30, 2017 at 2:36 AM, Michael Clark wrote:
>> Dear GCC folk,
>>
>>
>> # Issue Background
>>
>> We’re investigating an issue with redundant sign-extension instructions
>> being emitted with the riscv backend. Firstly I would
On Wed, Aug 30, 2017 at 2:36 AM, Michael Clark wrote:
> Dear GCC folk,
>
>
> # Issue Background
>
> We’re investigating an issue with redundant sign-extension instructions being
> emitted with the riscv backend. Firstly I would like to state that riscv is
> possibly a unique backend with respect
> On 30 Aug 2017, at 12:36 PM, Michael Clark wrote:
>
> Dear GCC folk,
>
>
> # Issue Background
>
> We’re investigating an issue with redundant sign-extension instructions being
> emitted with the riscv backend. Firstly I would like to state that riscv is
> possibly a unique backend with re
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