Eric Fisher <[EMAIL PROTECTED]> writes:
> Thanks for the help. Since ARM has condition codes, I'm wondering why it uses
> a psuedo register internally to represent things that use or set the
> condition codes?
> I think it should use CPSR directly.
ARM actually does use the CPSR directly. See CC
08 Oct 2005 10:40:40 -0700, Ian Lance Taylor :
> Eric Fisher <[EMAIL PROTECTED]> writes:
>
> > Who can explains for me about the comparison insns in mips.md.
>
> Look at the documentation for the bCOND instruction patterns.
>
> > One question, why there is only define_expand patterns but no
Eric Fisher <[EMAIL PROTECTED]> writes:
> Who can explains for me about the comparison insns in mips.md.
Look at the documentation for the bCOND instruction patterns.
> One question, why there is only define_expand patterns but no
> define_insn.
Because the gcc model for comparison inst
Hello,
Who can explains for me about the comparison insns in mips.md.
One question, why there is only define_expand patterns but no
define_insn. Supposed that I have a comparison instruction say 'cmp
%1, %2', should I implement define_insn patterns for comparison insns?
Here is a pattern fr
