o Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Pushing the limits on vector modes
>
> Quoting Paulo Matos :
>
> > Hello,
> >
> > I am trying to model a predicate register mode that acts like a
> > vector. We have a few predicate registers that have 8 bits in s
t: Re: Pushing the limits on vector modes
>
> Quoting Paulo Matos :
>
> > Hello,
> >
> > I am trying to model a predicate register mode that acts like a
> > vector. We have a few predicate registers that have 8 bits in size
> > but they are set accordingly t
Quoting Paulo Matos :
Hello,
I am trying to model a predicate register mode that acts like a
vector. We have a few predicate registers that have 8 bits in size
but they are set accordingly to the mode of operation (not
necessarily a comparison). Word size is 64.
Yes need some surgery
Hello,
I am trying to model a predicate register mode that acts like a vector. We have
a few predicate registers that have 8 bits in size but they are set accordingly
to the mode of operation (not necessarily a comparison). Word size is 64.
Here's an example, for a scalar comparison leq p0, r0,
