Hi,
> These other registers - r4 to r12 - are "callee saved".
To be precise, R4-R11 are callee-saved, R0-R3, R12, LR are caller-saves
and LR and PSR are clobbered by calls. LR is slightly odd in that it is
a callee-save in the prolog, but not in the epilog (since LR is assumed
clobbered after a c
On 16/11/17 17:54, Vitalijus Jefišovas wrote:
> On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
> other registers onto the psp stack, and then jumps to interrupt routine,
> when it finishes, NVIC restores these registers, and jumps back to user’s
> function.
> What is happen
Vitalijus Jefišovas kirjoitti 16.11.2017 klo 18:54:
On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
other registers onto the psp stack, and then jumps to interrupt routine,
when it finishes, NVIC restores these registers, and jumps back to user’s
function.
What is happenin
> On Nov 16, 2017, at 11:54 AM, Vitalijus Jefišovas wrote:
>
> On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
> other registers onto the psp stack, and then jumps to interrupt routine,
> when it finishes, NVIC restores these registers, and jumps back to user’s
> functio
On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
other registers onto the psp stack, and then jumps to interrupt routine,
when it finishes, NVIC restores these registers, and jumps back to user’s
function.
What is happening under the hood, NVIC only stacks 4 registers, r0, r1
