Re: Modifying RTL cost model to know about long-latency loads

2020-04-16 Thread Sasha Krassovsky via Gcc
Ahh I see, that makes a lot more sense. I’d want to change the TARGET_SCHED_ADJUST_PRIORITY hook? Also, would it still make sense to change the costs of expensive loads even during instruction selection to give opportunities for optimizations like rematerialization? I’m thinking that it could b

Re: Modifying RTL cost model to know about long-latency loads

2020-04-16 Thread Jim Wilson
On Thu, Apr 16, 2020 at 7:28 PM Sasha Krassovsky wrote: > @Jim I saw you were from SiFive - I noticed that modifying the costs for > integer multiplies in the riscv_tune_info structs didn’t affect the generated > code. Could this be why? rtx_costs is used for instruction selection. For instanc

Re: Modifying RTL cost model to know about long-latency loads

2020-04-16 Thread Sasha Krassovsky via Gcc
Thanks for your replies! I looked into the address spaces, and I think it’s easier to inform the RTX costs just using the attribute, but it was a good suggestion. Also, rtx_costs in rtlanal.c indeed seems to be the source of the problem. The SET expression does not look at the costs of its oper

Re: Modifying RTL cost model to know about long-latency loads

2020-04-13 Thread Jim Wilson
On Sat, Apr 11, 2020 at 4:28 PM Sasha Krassovsky via Gcc wrote: > I’m currently modifying the RISC-V backend for a manycore processor where > each core is connected over a network. Each core has a local scratchpad > memory, but can also read and write other cores’ scratchpads. I’d like to add >

Re: Modifying RTL cost model to know about long-latency loads

2020-04-11 Thread Alan Modra via Gcc
On Sat, Apr 11, 2020 at 04:27:07PM -0700, Sasha Krassovsky via Gcc wrote: > However, in the following example, the load does get the cost applied to it > but the store to B does not. > > void bar(__attribute__((remote(5)) int *a, int *b) > { > if(*A > 5) > *A = 10; > *B = *A; > }

Modifying RTL cost model to know about long-latency loads

2020-04-11 Thread Sasha Krassovsky via Gcc
Hello! I’m currently modifying the RISC-V backend for a manycore processor where each core is connected over a network. Each core has a local scratchpad memory, but can also read and write other cores’ scratchpads. I’d like to add an attribute to give a hint to the optimizer about which loads w