On Jan 27, 2014, at 8:59 AM, Paulo Matos wrote:
>> -Original Message-
>> From: Richard Sandiford [mailto:rsand...@linux.vnet.ibm.com]
>> Sent: 27 January 2014 16:50
>> To: Paulo Matos
>> Cc: gcc@gcc.gnu.org
>> Subject: Re: Mode change for bswap pat
> -Original Message-
> From: Richard Sandiford [mailto:rsand...@linux.vnet.ibm.com]
> Sent: 27 January 2014 16:50
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Mode change for bswap pattern expansion
>
> Sorry, I meant we use an unspec for the firs
Paulo Matos writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
>> Sent: 27 January 2014 16:06
>> To: Paulo Matos
>> Cc: gcc@gcc.gnu.org
>> Subject: Re: Mode change for bswap pattern expansion
>>
>>
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: 27 January 2014 16:06
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Mode change for bswap pattern expansion
>
> Paulo Matos writes:
> > On a vector processo
Paulo Matos writes:
> On a vector processor we can do a bswapsi with two instructions, by first
> rotating half-words (16 bits) by 8 and then rotating full words by 16.
> However, this means expanding:
> (set (match_operand:SI 0 "register_operand" "")
> (bswap:SI (match_operand:SI 1 "regist
Hello,
On a vector processor we can do a bswapsi with two instructions, by first
rotating half-words (16 bits) by 8 and then rotating full words by 16.
However, this means expanding:
(set (match_operand:SI 0 "register_operand" "")
(bswap:SI (match_operand:SI 1 "register_operand" "")))
to:
