On 10/07/11 09:50, BELBACHIR Selim wrote:
> (asm result)
>
> load d($C2),$R1 <--1st operand for comparison ctrl,readmem,nothing
> loadi 0,$C4 <- 2nd operand for comparison ctrl,nothing
> load d($C2+4),$R2 <--no data dependancies ctrl,readmem,nothing
> cmp $C4,$R1
Hello,
I'm trying to express the instruction latency time constraints of a private
processor.
* Overview :
Two cycles are necessary between a comparison instruction and a conditionnal
jump instruction (GSR is updated 2 cycles after comparison).
If nothing better than 'nop' can be used betwee
