On 06/22/10 13:18, Hans-Peter Nilsson wrote:
On Mon, 21 Jun 2010, Boris Boesler wrote:
The four instructions before the jump are placed into the
delay slots, such that the delay slots are completely filled;
but there is still the pipeline hazard, which can't be resolved
by inserting NOPs n
On Mon, 21 Jun 2010, Boris Boesler wrote:
> The four instructions before the jump are placed into the
> delay slots, such that the delay slots are completely filled;
> but there is still the pipeline hazard, which can't be resolved
> by inserting NOPs now, because there are no free slots.
GCC por
> Do I have to reorganize the code prior to slot filling? Do
> I have to make sure that some problematic instructions do
> not appear in slots?
Perhaps a easy way to solve the problem would be to claim for branches a memory
port a number of stages before and after the IF; to avoid in this way ha
In my backend GCC generates illegal scheduled code.
After pass sched2, GCC generates:
;;0--> 486 R1=R3<<0x4:IF,ID,AD,RA,EX,WB
;;1--> 487 A0=R1+`buffer':IF,ID,AD,RA,EX,WB
;;2--> 766 R0=abs(R7):IF,ID,
