DJ Delorie wrote:
Opening this up to the gcc public, since I appear to be unable to get
this to work right.
Still no luck defining a working IRA_COVER_CLASSES for m32c. My
latest attempt:
#define IRA_COVER_CLASSES \
{ \
HC_REGS, MEM_REGS, LIM_REG_CLASSES\
}
[ ... ]
I actually got a
> Sure, DJ. I'll look at this but unfortunately I can do it on next week
> because I am busy with numerous other IRA bugs.
Next week would be fine :-)
> As I wrote m32c is pretty nasty case and may be will need even insn
> description changes.
I'm OK with that.
DJ Delorie wrote:
Opening this up to the gcc public, since I appear to be unable to get
this to work right.
Still no luck defining a working IRA_COVER_CLASSES for m32c. My
latest attempt:
#define IRA_COVER_CLASSES \
{ \
HC_REGS, MEM_REGS, LIM_REG_CLASSES\
}
(effectively GENERAL_REGS
> I think our mxp is more 'interesting'. [snip]
I think it's more like 'insane', :-) and a miracle that a retargetable
compiler can be ported to it.
Paolo
As I've said before, m32c is probably a "worst case" scenario for gcc
as it has not one, not two, not even three, but FOUR different types
of registers (8/16 bit general, 16 bit only general, 24 bit address
registers, and control (incl $fp) registers), and only a small number
(2) of each.
I think
DJ Delorie wrote:
Opening this up to the gcc public, since I appear to be unable to get
this to work right.
Still no luck defining a working IRA_COVER_CLASSES for m32c. My
latest attempt:
#define IRA_COVER_CLASSES \
{ \
HC_REGS, MEM_REGS, LIM_REG_CLASSES\
}
(effectively GENERAL_REGS
Opening this up to the gcc public, since I appear to be unable to get
this to work right.
Still no luck defining a working IRA_COVER_CLASSES for m32c. My
latest attempt:
#define IRA_COVER_CLASSES \
{ \
HC_REGS, MEM_REGS, LIM_REG_CLASSES\
}
(effectively GENERAL_REGS (which I also tried
