On 04/27/2012 11:31 PM, Greg McGary wrote:
I'm working on a port that does loads& stores in two phases.
Every load/store is funneled through the intermediate registers "ld" and "st"
standing between memory and the rest of the register file.
Example:
ld=4(rB)
...
...
I think this is what secondary reload is for. Check the internals manual.
Something like this shows up in the pdp11 port, where float registers f4 and f5
can't be loaded/stored directly. You can see in that port how this is handled;
it seems to work.
paul
On Apr 27, 2012, at 5:31 PM,
On 04/27/12 14:31, Greg McGary wrote:
> I'm working on a port that does loads & stores in two phases.
> Every load/store is funneled through the intermediate registers "ld" and "st"
> standing between memory and the rest of the register file.
>
> Example:
> ld=4(rB)
> ...
>
I'm working on a port that does loads & stores in two phases.
Every load/store is funneled through the intermediate registers "ld" and "st"
standing between memory and the rest of the register file.
Example:
ld=4(rB)
...
...
rC=ld
st=rD
8(rB)=st
rB
