Quoting Tom de Vries :
About the penalty, I don't really know. But since the optimization is
both filling delay slots and removing
duplicate code, it looks like a good idea to me.
It's usually beneficial, but for some microarchitectures, this kind of
code confuses the branch predictor.
So ther
Hi Jeff,
However, that doesn't work for the second example:
...
beq$3,$0,$L14
nop
$L7:
andi$2,$2,0x
...
bne$3,$0,$L7
nop
$L14:
andi$2,$2,0x
...
...
What is different from the first example, is that here the beq owns
neither the
fall-throug
On 11/18/10 10:31, Tom de Vries wrote:
I'm working on improving delay-slot scheduling and would appreciate
advice on a
problem I encountered.
Oh boy
The problem is: how to add support for placing a CODE_LABEL on an
instruction in
a delay slot?
My impression is that this is not support
I'm working on improving delay-slot scheduling and would appreciate
advice on a
problem I encountered.
The problem is: how to add support for placing a CODE_LABEL on an
instruction in
a delay slot?
My impression is that this is not supported currently. One way to
implement this
would be to a
