On 23/10/11 22:21, Richard Henderson wrote:
On 10/21/2011 05:49 PM, paul_kon...@dell.com wrote:
There are lots of parts of the compiler that don't optimize well when an insn
has more than one output. For the normal insn, just clobber the flags; don't
include a second SET.
Yes, but... isn't
On 21/10/11 22:41, Richard Henderson wrote:
On 10/21/2011 10:15 AM, Paulo J. Matos wrote:
So I have implemented the nadd and addc as:
(define_insn "negqi2"
[(set (match_operand:QI 0 "register_operand" "=c")
(neg:QI (match_operand:QI 1 "register_operand" "0")))
(set (reg:CC_C RCC
On 10/21/2011 05:49 PM, paul_kon...@dell.com wrote:
>> There are lots of parts of the compiler that don't optimize well when an
>> insn has more than one output. For the normal insn, just clobber the flags;
>> don't include a second SET.
>
> Yes, but... isn't the whole point of CC modeling that
>There are lots of parts of the compiler that don't optimize well when an insn
>has more than one output. For the normal insn, just clobber the flags; don't
>include a second SET.
Yes, but... isn't the whole point of CC modeling that you can take advantage of
the CC left around by an instructi
On Fri, Oct 21, 2011 at 4:41 PM, Richard Henderson wrote:
> On 10/21/2011 10:15 AM, Paulo J. Matos wrote:
>> So I have implemented the nadd and addc as:
>>
>> (define_insn "negqi2"
>> [(set (match_operand:QI 0 "register_operand" "=c")
>> (neg:QI (match_operand:QI 1 "register_operand" "0"
On 10/21/2011 10:15 AM, Paulo J. Matos wrote:
> So I have implemented the nadd and addc as:
>
> (define_insn "negqi2"
> [(set (match_operand:QI 0 "register_operand" "=c")
> (neg:QI (match_operand:QI 1 "register_operand" "0")))
>(set (reg:CC_C RCC) (eq (match_dup 1) (const_int 0)))
>
On 19/10/11 01:48, paul_kon...@dell.com wrote:
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of Richard
Henderson
On 10/17/2011 03:50 AM, Paulo J. Matos wrote:
...
(for example, it would be ok to output negqi2, xorqi3 and
addc_internal since xorqi3 only sets N and Z, not
On 10/21/2011 09:13 AM, Peter Bigot wrote:
> Are there any existing machine descriptions that do model the carry
> flag separately, specifically to model rotate operations that use the
> carry flag as the destination and source for the shifted bit? Or is
> the best I can do for that is to have the
On 19/10/11 00:10, Richard Henderson wrote:
The thing that's almost certainly missing is that the NAND pattern
must SET your flags register, not simply clobber it. Otherwise the
dependency between the ADDC and the NAND will never be created properly.
I understand that there's a missing SET o
>From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
>Richard Henderson
>On 10/17/2011 03:50 AM, Paulo J. Matos wrote:
>>...
>> (for example, it would be ok to output negqi2, xorqi3 and
>> addc_internal since xorqi3 only sets N and Z, not the Carry bit)
>
>For that you'd have
On 10/17/2011 03:50 AM, Paulo J. Matos wrote:
> Hi,
>
> To negate a double word (HImode) register, I used to take the instruction all
> the way to assembly generation and then expand into three assembly
> instructions like so:
> xor %t0, # ; invert bits in top word of op0
> nadd %b0, #0
On 17/10/11 17:20, Andrew Pinski wrote:
On Mon, Oct 17, 2011 at 3:50 AM, Paulo J. Matos wrote:
addc_internal looks like:
(define_insn "addc_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=c")
(plus:QI
(plus:QI
(ltu:QI (reg:CC RCC) (const_int 0))
On Mon, Oct 17, 2011 at 3:50 AM, Paulo J. Matos wrote:
> addc_internal looks like:
> (define_insn "addc_internal"
> [(set (match_operand:QI 0 "nonimmediate_operand" "=c")
> (plus:QI
> (plus:QI
> (ltu:QI (reg:CC RCC) (const_int 0))
> (match_operand:QI 1 "noni
Hi,
To negate a double word (HImode) register, I used to take the
instruction all the way to assembly generation and then expand into
three assembly instructions like so:
xor %t0, # ; invert bits in top word of op0
nadd %b0, #0; negate bottom bits of op0
addc %t0, #0; add ca
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