"Radu Hobincu" writes:
> I have 16 vectorial registers in the machine R16-R31 which all have 128
> cells of 16 bits each. These support ALU operations and load/stores just
> as normal registers, but in one clock. So an
>
> add R16 R17 R18
>
> will add the whole R17 array with R18 (corresponding c
I have 16 vectorial registers in the machine R16-R31 which all have 128
cells of 16 bits each. These support ALU operations and load/stores just
as normal registers, but in one clock. So an
add R16 R17 R18
will add the whole R17 array with R18 (corresponding cells) and place the
result in R1
> "Radu Hobincu" writes:
>
>> However, now I have another problem. I have 2 instructions in the ISA:
>> 'where' and 'endwhere' which modify the behavior of the instructions put
>> in between them. I made a macro with inline assembly for each of them.
>> The
>> problem is that since `endwhere` does
"Radu Hobincu" writes:
> However, now I have another problem. I have 2 instructions in the ISA:
> 'where' and 'endwhere' which modify the behavior of the instructions put
> in between them. I made a macro with inline assembly for each of them. The
> problem is that since `endwhere` doesn't have a
if I waste too much of your time with random
questions, tell me and I will stop. :)
Regards,
R.
> "Radu Hobincu" writes:
>
>> I have another, quick question: I have dedicated logical instructions
in
>> my RISC machine (lt - less than, gt - greater than, ult - unsigned l
"Radu Hobincu" writes:
> I have another, quick question: I have dedicated logical instructions in
> my RISC machine (lt - less than, gt - greater than, ult - unsigned less
> than, etc.). I'm also working on adding instructions for logical OR, AND,
> NOT, XOR. While
Hello again,
I have another, quick question: I have dedicated logical instructions in
my RISC machine (lt - less than, gt - greater than, ult - unsigned less
than, etc.). I'm also working on adding instructions for logical OR, AND,
NOT, XOR. While reading GCC internals, I've stumbl
