Matt Lee writes:
> In any case, I am trying to optimize the case where there is clearly no
> aliasing. Your suggestion regarding movmemsi is interesting. I have not used
> this pattern before and assumed that it was required only when something
> special must be done to do block moves. In my archit
On 8/31/07, Adam Nemet <[EMAIL PROTECTED]> wrote:
> "Matt Lee" <[EMAIL PROTECTED]> writes:
>
> > I am seeing poor scheduling in Dhrystone where a memcpy call is
> > expanded inline.
> >
> > memcpy (&dst, &src, 16) ==>
> >
> > load 1, rA + 4
> > store 1, rB + 4
> > load 2, rA + 8
> > store 2, rB +
---
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Matt Lee
> Sent: 2007年9月1日 5:58
> To: gcc@gcc.gnu.org
> Subject: DFA Scheduler - unable to pipeline loads
>
> Hi,
>
> I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
> RISC processors wi
Matt Lee wrote:
Hi,
I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
RISC processors with the following description for loads and stores,
(define_insn_reservation "integer" 1
(eq_attr "type" "branch,jump,call,arith,darith,icmp,nop")
"issue,iu,wb")
(define_insn_reservation
by "," should be equal to latency. Am I right?
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Matt Lee
Sent: 2007年9月1日 5:58
To: gcc@gcc.gnu.org
Subject: DFA Scheduler - unable to pipeline loads
Hi,
I am working with GCC-4.1.1 on
"Matt Lee" <[EMAIL PROTECTED]> writes:
> I am seeing poor scheduling in Dhrystone where a memcpy call is
> expanded inline.
>
> memcpy (&dst, &src, 16) ==>
>
> load 1, rA + 4
> store 1, rB + 4
> load 2, rA + 8
> store 2, rB + 8
> ...
Are you sure that there are no dependencies due to aliasing h
Hi,
I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
RISC processors with the following description for loads and stores,
(define_insn_reservation "integer" 1
(eq_attr "type" "branch,jump,call,arith,darith,icmp,nop")
"issue,iu,wb")
(define_insn_reservation "load" 3
(eq_at
