Correction,
...compare:CC_N... (R1:HI, 0)
On 05/09/14 09:31, Paul Shortis wrote:
Thanks Richard,
I found the bug. try_eliminate_compare follows register
definitions between the flags use and the clobbering compare by
register number only, i.e. the register width isn't considered.
if (D
Thanks Richard,
I found the bug. try_eliminate_compare follows register
definitions between the flags use and the clobbering compare by
register number only, i.e. the register width isn't considered.
if (DF_REF_REGNO (def) == REGNO (in_a))
break;
This caused R1:HI to follow R0:SI c
On 09/03/2014 03:14 PM, Paul Shortis wrote:
> (insn 33 84 85 6 (parallel [
> (set (reg:HI 1 r1)
> (ashift:HI (reg:HI 1 r1)
> (const_int 1 [0x1])))
> (clobber (reg:CC_NOOV 7 flags))
> ]) ../gcc/testsuite/gcc.c-torture/execute/960311
Hello!
> While I'm here, in i386.md some of the flag setting operations specify a mode
> and some don't . Eg
>
> (define_expand "cmp_1"
> [(set (reg:CC FLAGS_REG)
> (compare:CC (match_operand:SWI48 0 "nonimmediate_operand")
>
>
> (define_insn "*add_3"
> [(set (reg FLAGS_REG)
> (compar
For a 16 bit CPU the cmpelim pass is changing
(insn 33 84 85 6 (parallel [
(set (reg:HI 1 r1)
(ashift:HI (reg:HI 1 r1)
(const_int 1 [0x1])))
(clobber (reg:CC_NOOV 7 flags))
]) ../gcc/testsuite/gcc.c-torture/execute/960311-3.c:18
