Hi Claudiu,
On Fri, Nov 17, 2017 at 03:05:23PM +, Claudiu Zissulescu wrote:
> I've found a potential issue when performing CFG operations for hardware
> loops.
>
> When a port is using hardware loops (like ARC) makes use of reorg_loops to
> find and analyze loops that end in loop_end instru
Hi,
I've found a potential issue when performing CFG operations for hardware loops.
When a port is using hardware loops (like ARC) makes use of reorg_loops to find
and analyze loops that end in loop_end instructions. The very same function can
be set to reorder the cfg such that the loop end oc
