> On 5 Sep 2017, at 9:35 AM, Michael Clark wrote:
>
>>
>> On 19 Aug 2017, at 4:10 AM, Richard Henderson wrote:
>>
>> On 08/17/2017 03:29 PM, Michael Clark wrote:
>>> hand coded x86 asm (no worse because the sar depends on the lea)
>>>
>>> sx5(int):
>>> shl edi, 27
>>> sar edi
> On 19 Aug 2017, at 4:10 AM, Richard Henderson wrote:
>
> On 08/17/2017 03:29 PM, Michael Clark wrote:
>> hand coded x86 asm (no worse because the sar depends on the lea)
>>
>> sx5(int):
>>shl edi, 27
>>sar edi, 27
>>movsx eax, dl
>
> Typo in the register, but I k
On 08/17/2017 03:29 PM, Michael Clark wrote:
> hand coded x86 asm (no worse because the sar depends on the lea)
>
> sx5(int):
> shl edi, 27
> sar edi, 27
> movsx eax, dl
Typo in the register, but I know what you mean. More interestingly, edi
already has the sign-ext
On Fri, 2017-08-18 at 10:29 +1200, Michael Clark wrote:
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed
> by SAR trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice.
> In any case RISC-V seems l
On Fri, Aug 18, 2017 at 10:56:10PM +1200, Michael Clark wrote:
>
> > On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
> >
> > On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
> >> Sorry I had to send again as my Apple mailer is munging emails. I’ve
> >> disabled RTF.
> >>
> >>
> On 18 Aug 2017, at 10:56 PM, Michael Clark wrote:
>
>>
>> On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
>>
>> On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
>>> Sorry I had to send again as my Apple mailer is munging emails. I’ve
>>> disabled RTF.
>>>
>>>
>>> This o
> On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
>
> On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
>> Sorry I had to send again as my Apple mailer is munging emails. I’ve
>> disabled RTF.
>>
>>
>> This one is quite interesting:
>>
>> - https://cx.rv8.io/g/WXWMTG
>>
>>
On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
> Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled
> RTF.
>
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed by
> On 18 Aug 2017, at 11:13 AM, Michael Clark wrote:
>
> So it is a bug on arm too? and can be done with one sbfiz instruction?
> (assuming I’m understand sbfiz from my first reading) e.g.
>
> sbfiz w0, w0, 0, 2
>ret
Getting my 3’s and 5’s swapped. Confused by gcc.
sbfiz w0,
> On 18 Aug 2017, at 10:41 AM, Andrew Pinski wrote:
>
> On Thu, Aug 17, 2017 at 3:29 PM, Michael Clark wrote:
>> Sorry I had to send again as my Apple mailer is munging emails. I’ve
>> disabled RTF.
>>
>>
>> This one is quite interesting:
>>
>> - https://cx.rv8.io/g/WXWMTG
>>
>> It’s anoth
On Thu, Aug 17, 2017 at 3:29 PM, Michael Clark wrote:
> Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled
> RTF.
>
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed by SAR
> tric
Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled
RTF.
This one is quite interesting:
- https://cx.rv8.io/g/WXWMTG
It’s another target independent bug. x86 is using some LEA followed by SAR
trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice. In any case
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