Hi Bruce,
Thanks for your sharing!
I am porting GlobalISel to RISCV target[1], the highest priority in the
TODO list[2], welcome to contribute to lowRISC, if fixed all the issues,
then I could try to implement RegAllocGraphColoring in HEA and write
great Machine Schedulers.
[1] https://gith
So, both AVR and RISC-V are fairly register-rich with usually 32. RV32E
only has 16, but that's still a lot better than i386. If you use a lot of
16 bit integers then AVR also only has effectively 16 registers (or a more
with a mix of 8 and 16 bit variables). 32 bit integers should be rare in
AVR c
> On Dec 18, 2017, at 8:16 PM, Vladimir Makarov via llvm-dev
> wrote:
>
>
>
> On 12/18/2017 07:07 PM, Michael Clark wrote:
>> Hi Leslie,
>>
>> I suggest adding these 3 papers to your reading list.
>>
>> Register allocation for programs in SSA-form
>> Sebastian Hack, Daniel Grund,
Hi Matthias,
Thanks for your hint!
It is just for learning and practicing for me, just like migrate
DragonEgg
http://lists.llvm.org/pipermail/llvm-dev/2017-September/117201.html the
motivating is for learning from GCC and LLVM developers.
在 2017年12月19日 10:07, Matthias Braun 写道:
On Dec 1
