On Thu, Jan 06, 2011 at 09:59:08AM +0200, Revital1 Eres wrote:
> Index: loop-doloop.c
> + Some targets (ARM) do the comparison before the branch, as in the
> + folloring form:
^
"following"
> + /* In case the pattern is not PARALLEL we expect two forms
> + of dol
>> Index: config/arm/thumb2.md
>> ===
>> --- config/arm/thumb2.md (revision 168424)
>> +++ config/arm/thumb2.md (working copy)
>
>> + ??? The possible introduction of a new block to initialize the
>> + new IV can po
Revital1 Eres writes:
> Index: loop-doloop.c
> ===
> --- loop-doloop.c (revision 168397)
> +++ loop-doloop.c (working copy)
> + /* The third case: the compre and decrement instructions
s/compre/compare/.
> Index: con
Hello,
>
> @@ -162,6 +175,7 @@ doloop_condition_get (rtx doloop_pat)
> return 0;
>
>if ((XEXP (condition, 0) == reg)
> + || (REGNO (XEXP (condition, 0)) == CC_REGNUM)
>|| (GET_CODE (XEXP (condition, 0)) == PLUS
>&& XEXP (XEXP (condition, 0), 0) == reg))
>
ch and it's not in the proper format of
> submission yet.
>
> Thanks,
> Revital
>
> (See attached file: patch_arm_doloop.txt)
>
>
>
> From: Roman Zhuykov
> To: gcc@gcc.gnu.org
> Cc: d...@ispras.ru
> Date: 30/12/2010 04:04 PM
> Su
p.txt)
From: Roman Zhuykov
To: gcc@gcc.gnu.org
Cc: d...@ispras.ru
Date: 30/12/2010 04:04 PM
Subject: [ARM] Implementing doloop pattern
Sent by:gcc-ow...@gcc.gnu.org
Hello!
The main idea of the work described below was to estimate speedup we can
gain from SMS on ARM.
Roman Zhuykov wrote:
> Memory is used instead of a register to store doloop counter.
Yes, this can happen, and your doloop insn pattern *must* be
able to handle this. This is usually done via a splitter
(and possibly an additional scratch register allocated via
an extra insn operand). See vario
Hello!
The main idea of the work described below was to estimate speedup we can
gain from SMS on ARM. SMS depends on doloop_end pattern and there is no
appropriate instruction on ARM. We decided to create a "fake"
doloop_end pattern on ARM using a pair of "subs" and "bne" assembler
instruct
