ards
> Alex
>
>> On Jan 23, 2024, at 8:42 AM, jacob navia via Gcc wrote:
>>
>> Hi
>> The GNU assembler supports two instructions for the T-Head risk machines
>> called:
>>
>> th.ipop
>> th.ipush
>>
>> With no arguments. Thes
Hi
The GNU assembler supports two instructions for the T-Head risk machines called:
th.ipop
th.ipush
With no arguments. These instructions (they are no macros or aliases) are
UNDOCUMENTED in the T-Head instruction manuals that I have, and a google search
yields absolutely nothing.
Can anyone h
Hi
I have foujnd the reason for the weird behavior of gcc when reading 64 bits
data.
I found out how to avoid this. The performance of the generated code doubled.
I thank everyone in this forum for their silence to my repeated help requests.
They remind me that:
THE ENTIRE RISK AS TO THE QUAL
Hi
In a previous post I pointed to a strange code generation`by gcc in the
riscv-64 targets.
To resume:
Suppose a 64 bit operation: c = a OP b;
Gcc does the following:
Instead of loading 64 bits from memory gcc loads 8 bytes into 8
separate registers for both operands. Then it ORs
Hi
Looking at the code generated by the riscv backend:
Consider this C source code:
void shup1(QfloatAccump x)
{
QELT newbits,bits;
int i;
bits = x->mantissa[9] >> 63;
x->mantissa[9] <<= 1;
for( i=8; i>0; i-- ) {
newbits = x->mantissa[i] >>
