how to optimize address offset assignment

Hi, everyone: The address mode in my my RISC chip is like (BaseReg) + 8bit offset, or (BaseReg) + indexReg. And there a 16 general register from R0 to R15 which can be used as Base register or Index Regster. So you can see that if the frame space is larger than 255, there will be a problem. F

RE: How to deal with unrecognizable RTL code

legitimate address: mem/s:SI (plus:SI (reg/v/f:SI 91 [ frame ]) (const_int 4 [0x4])) Of course it is not a valid address in strict mode. And a logical error was found in my rice_reg_ok_for_base function. After fixing it, cc1 works well . Thank you very much! Daniel.tian

RE: How to deal with unrecognizable RTL code

> Which means that reg 91 was spilled (ie, it did not get a hard register > assigned). You can verify this by looking at reg_equiv_mem[91] just > before this loop in reload1.c: > > /* This loop scans the entire function each go-round > and repeats until one repetition spills no additional hard reg

RE: How to deal with unrecognizable RTL code

> This looks like a different problem. What pass generates insn 17? What > does insn 17 look like in the prior pass? If r14 is your stack/frame > pointer, this might point to a problem in how your port interacts with > register allocation/reload as reload can replace a pseudo with an > equivalent m

Re:How to deal with unrecognizable RTL code

Hi, I check the MIPS and ARM, both those cc1 files opened in Insight debug tool contain the mips.md and arm.md file. It is convenient while break point can be set in it. My port md file doesn't appear in the insight. How can I make it? ___ Best Regards

答复: How to deal with unrecognizable RTL code

cation in (mem/f:SI (plus:SI (reg/f:SI 14 R14) (const_int 172 [0xac])) is R5. I don't why it is placed and what criteria the displacement bases. Does Gcc like to merge some RTL? If it does, gcc merge RTL base what? I mean if the merging happening, some generating RT

re: How to deal with unrecognizable RTL code

Hi: >> 1) does your machine use cc0? No. In my RISC chip, there is a status register existed, like ARM. But I now I didn't write any code to support it, as well as absent cc0 register. >> 2) what pass is producing those subregs? This is really puzzled me. I just wrote the PROMOTE_MODE like MIP

re: How to deal with unrecognizable RTL code

there to force them into specified way. Any suggestion is appreciated! Thank you very much! Daniel.Tian ___ Best Regards Daniel Tian Tel:86(21)51095958 - 8125 Fax:86(21)50277658 email：daniel.t...@mavrixtech.com.cn www.mavrixtech.com -- Regards, Paul Yuan (袁鹏)