Hi Bin,
> -Original Message-
> From: gcc-ow...@gcc.gnu.org On Behalf Of
> Bin.Cheng
> Sent: Sunday, November 11, 2018 12:28 PM
> To: GCC Development
> Subject: A GCC bug related to inline?
>
> Hi,
> Given below simple code:
>
> inline int foo (int a) {
> return a + 1;
> }
> int g = 5
Hi
> -Original Message-
> From: NightStrike [mailto:nightstr...@gmail.com]
> Sent: Monday, May 2, 2016 10:31 PM
> To: Kumar, Venkataramanan
> Cc: Uros Bizjak (ubiz...@gmail.com) ;
> lopeziba...@gmail.com; Jan Hubicka ; Jakub Jelinek
> ; gcc@gcc.gnu.org
> Subject
Hi,
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> NightStrike
> Sent: Monday, May 2, 2016 1:55 AM
> To: gcc@gcc.gnu.org
> Cc: Jan Hubicka ; Jakub Jelinek
> Subject: option -mprfchw on 2 different Opteron cpus
>
> Reposting from here:
>
Hi,
> -Original Message-
> From: Ilya Enkovich [mailto:enkovich@gmail.com]
> Sent: Wednesday, April 27, 2016 5:35 PM
> To: Kumar, Venkataramanan
> Cc: vmaka...@redhat.com; gcc@gcc.gnu.org; Uros Bizjak
> (ubiz...@gmail.com)
> Subject: Re: Quest
Hi ,
> -Original Message-
> From: Ilya Enkovich [mailto:enkovich@gmail.com]
> Sent: Tuesday, April 26, 2016 7:09 PM
> To: Kumar, Venkataramanan
> Cc: vmaka...@redhat.com; gcc@gcc.gnu.org; Uros Bizjak
> (ubiz...@gmail.com)
> Subject: Re: Quest
Hi,
X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE regs instead
of memory.
I tried enabling the above tuning with -march=bdver4 -Ofast
-mtune-ctrl=general_regs_sse_spill.
I did not find any code differences.
Looking at the below code to enable this tune, mmx ISA needs to b
Hi,
> -Original Message-
> From: Tom de Vries [mailto:tom_devr...@mentor.com]
> Sent: Tuesday, April 12, 2016 3:09 PM
> To: Kumar, Venkataramanan
> Cc: gcc Development ; Sebastian Pop
>
> Subject: Re: Building gcc with graphite
>
> [ cc-ing gcc ml ]
&g
Hi ,
For the below code x86_64 is able to vectorize.
#define LEN 32000
__attribute__((aligned(32))) float a[LEN], b[LEN],c[LEN]; void test() { for
(int i = 0; i < LEN; i++) {
if (b[i] > (float)0.) {
a[i] = b[i];
}
}
}
X86_64 ASM
L2:
vmovaps b(%rax), %ymm0
2 PM
> To: Kumar, Venkataramanan
> Cc: gcc@gcc.gnu.org
> Subject: Re: parameters to _mm_mwait intrinsic
>
> On Wed, Jun 3, 2015 at 2:47 PM, Kumar, Venkataramanan
> wrote:
> > Hi,
> >
> > I was going through the "monitor" and "mwait" builtin imp
Hi,
I was going through the "monitor" and "mwait" builtin implementation.
I need clarification on the parameters passed to _mm_mwait intrinsic.
We have the following defined in "pmmintrin.h"
extern __inline void __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_monitor (vo
Hi Bing,
Yes I am planning to continue it after stage 1 opens.
Regards,
Venkat.
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
Bin.Cheng
Sent: Friday, April 03, 2015 7:16 AM
To: Jeff Law
Cc: gcc@gcc.gnu.org
Subject: Re: Combine changes ASHIFT
> -Original Message-
> From: Richard Guenther [mailto:richard.guent...@gmail.com]
> Sent: Monday, February 20, 2012 4:58 PM
> To: gcc@gcc.gnu.org
> Cc: Kumar, Venkataramanan
> Subject: Re: [i386] Question about Constraint Modifier character in smaxdf3
> pattern.
>
Hi all,
Sphinx3 benchmark segmented when built and ran with -Ofast and
-fprefecth-loop-arrays.
When I debugged the benchmark executable, found that it is caused due to
register swapping happening
at reload for the smaxdf3 pattern.
197r.ira
-
(insn 457 456 458 28 (set (reg:DF 687)
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