Re: MIPS: Changing the PC stored from a "and link" instruction

PC of the first instruction of .cpload into $ra (the instruction after bal), then .cpload still functions correctly. -Brandon On 02/18/2011 01:43 AM, Ian Lance Taylor wrote: "Brandon H. Dwiel" writes: I would like to make the changes necessary so that the compiler expects the

MIPS: Changing the PC stored from a "and link" instruction

Hello, I am a student working on a project involving generating a MIPS processor. We have decided to NOT implement logic to handle branch delay slots and instead work with generating a compiler that will emit code without these delay slots. The compiler tool chain versions are: binutils: 2.