On Wed, 2007-10-17 at 12:58 +0930, Alan Modra wrote:
> On Tue, Oct 16, 2007 at 08:21:55PM +0200, Jakub Jelinek wrote:
> > On Tue, Oct 16, 2007 at 06:02:13PM +0100, Andrew Haley wrote:
> > > The reason is that the unwinder data for CR in the vDSO is wrong. The
> > > line that affects the CR is her
> Surely it would be possible to use -ffixed-* options to reserve all the
> altivec registers and get precisely that effect?
Nah, I don't need to be that drastic. The RAID6 code is already in a
separate file that can have a specific additional set of compile flags,
so I can just enable altivec
On Sun, 2005-02-27 at 19:32 -0500, David Edelsohn wrote:
> >>>>> Benjamin Herrenschmidt writes:
>
> Ben> The only problem I see is that the day we have a CPU, let's call it
> Ben> POWER8 for the sake of this demonstration, that has altivec and is
> Be
On Sun, 2005-02-27 at 18:56 -0500, David Edelsohn wrote:
> >>>>> Benjamin Herrenschmidt writes:
>
> Ben> Ok. What I need is -mcpu=power4 -maltivec
>
> Sorry, no. -maltivec means generate Altivec code, not just enable
> Altivec instructions and registers
On Sun, 2005-02-27 at 18:40 -0500, Andrew Pinski wrote:
> On Feb 27, 2005, at 6:35 PM, David Edelsohn wrote:
>
> > As Andrew Pinski mentioned, you also can use -mcpu=970
> > -mno-altivec. That should allow the assembler to accept Altivec
> > instructions, but GCC will not know about any Altiv
> Yes, but as I wrote, that prevents building the RAID6 code which
> contains some selected altivec bits and cause gas to not get passed the
> proper option so we can have instructions like "dssall" in the low level
> assembly files.
>
> The later can probably be worked around by adding the prope
On Sun, 2005-02-27 at 17:53 -0500, David Edelsohn wrote:
> >>>>> Benjamin Herrenschmidt writes:
>
> Ben> There seem to be a problem with gcc 4.0 and implicit generation of
> Ben> altivec instructions when -mcpu=970.
>
> Ben> The problem is th
On Sun, 2005-02-27 at 17:47 -0500, Andrew Pinski wrote:
> s the proper way or set of options for me to:
> >
> > 1) optionally have POWER4 optimisations (that must be independant on
> > the rest below)
> > 2) be able to use altivec instructions in assembly
> > 3) be able to use altivec in a few s
Hi !
There seem to be a problem with gcc 4.0 and implicit generation of
altivec instructions when -mcpu=970.
The problem is that the kernel cannot afford to use altivec instructions
(nor FPU) except in controlled environment. Specifically, things like
the RAID6 code has altivec (and SSE/2, which
