Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387. The idea was to allow
use of i387 registers when SSE ones run out and possibly also model the fact
that Pentium4 had faster i387 additions than SSE additions. I also ha
Hello all,
With gcc, does the fact that some branch results in a C++ exception
effect the performance of a function when that exception branch isn't
entered? In other words, does the presence of a throw effect the
optimizer in any way?
-- David Sankel
--
David Sankel
Stellar Science Ltd Co
2015-04-24 13:27 GMT+03:00 Marc Glisse :
> On Fri, 24 Apr 2015, Uros Bizjak wrote:
>
>> Please try to generate paradoxical subreg (V2DImode subreg of V1DImode
>> pseudo). IIRC, there is some functionality in the compiler that is
>> able to tell if the highpart of the paradoxical register is zeroed.
On Fri, 24 Apr 2015, Uros Bizjak wrote:
Please try to generate paradoxical subreg (V2DImode subreg of V1DImode
pseudo). IIRC, there is some functionality in the compiler that is
able to tell if the highpart of the paradoxical register is zeroed.
Those are not currently legal (I tried to change
On Fri, Apr 24, 2015 at 12:14 PM, Uros Bizjak wrote:
> I was looking into PR65105 and tried to generate SSE computation for a
> simple 64bit a + b + c sequence. Having no scalar integer instructions in
> SSE I have to use vector variants.
Is this approach really better that
On Fri, Apr 24, 2015 at 12:09 PM, Ilya Enkovich wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions in
SSE I have to use vector variants.
>>>
>>> Is this approach really better that ha
2015-04-24 12:49 GMT+03:00 Uros Bizjak :
> On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak wrote:
>> On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich
>> wrote:
>>
>>> I was looking into PR65105 and tried to generate SSE computation for a
>>> simple 64bit a + b + c sequence. Having no scalar intege
2015-04-24 12:45 GMT+03:00 Uros Bizjak :
> On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich
> wrote:
>
>> I was looking into PR65105 and tried to generate SSE computation for a
>> simple 64bit a + b + c sequence. Having no scalar integer instructions in
>> SSE I have to use vector variants.
>
> I
On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak wrote:
> On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich
> wrote:
>
>> I was looking into PR65105 and tried to generate SSE computation for a
>> simple 64bit a + b + c sequence. Having no scalar integer instructions in
>> SSE I have to use vector va
On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich wrote:
> I was looking into PR65105 and tried to generate SSE computation for a
> simple 64bit a + b + c sequence. Having no scalar integer instructions in
> SSE I have to use vector variants.
Is this approach really better that having two add/add
Hi,
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer
instructions in SSE I have to use vector variants.
Original RTL:
(insn 3 2 4 2 (set (reg/v:DI 91 [ b ])
(mem/c:DI (plus:SI (reg/f:SI 16 argp)
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