As some may have seen I posted a patch to gcc-patches that adds a way to
embed GCC as a shared library, for Just-In-Time compilation, for use
e.g. by bytecode interpreters:
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg00228.html
I've gone ahead and created a git-only on the mirror as branch
"dma
Some observations:
* Various source files include x86-specific asm. At some point it will
need restructuring so that the architecture-specific parts go in
architecture-specific files and it's clear what to do to add support for
another architecture.
* Given that architecture dependency, the t
Dear Jeff and the rest of Steering committee members,
Thank you very much for approving the license terms of the Cilk Library. I
couldn't attach the zipped copy of the patch due to its size, so here is a link
to the Cilk library patch that can be applied to the trunk:
(https://docs.google.c
Hi,
www.x86-64.org was down for several months and it is up
now, but not in its full capacity. I created a x86-64 psABI
group:
https://groups.google.com/forum/?hl=en#!forum/x86-64-abi
so that there is a mailing list we can discuss x86-64 psABI
related issues.
Thanks.
--
H.J.
On Oct 9, 2013, at 5:24 AM, Umesh Kalappa wrote:
> Dear Group ,
>
> We are re-targeting the GCC to the CISC target ,which has the eight
> 8-bit registers and same register set can used as pair register for
> 16 bit computation i.e four 16-bits .
>
> Any one in the group tell me ,How do i
Status
==
The GCC 4.8.2-rc1 release candidate has been released.
The branch is frozen now, all changes require release manager approval
until the final release of GCC 4.8.2 which should happen roughly
one week after the release candidate.
Quality Data
Priority # Chan
The first release candidate for GCC 4.8.2 is available from
ftp://gcc.gnu.org/pub/gcc/snapshots/4.8.2-RC-20131009
and shortly its mirrors. It has been generated from SVN revision 203308.
I have so far bootstrapped and tested the release candidate on
x86_64-linux and i686-linux. Please test
On Wed, Oct 09, 2013 at 10:56:33AM +0100, Richard Sandiford wrote:
> gcc/testsuite/
> * gcc.target/i386/asm-rename-1.c: New file.
>
> Index: gcc/testsuite/gcc.target/i386/asm-rename-1.c
> ===
> --- /dev/null 2013-10-09 10:21:20.
Jakub Jelinek writes:
> On Wed, Oct 09, 2013 at 10:59:35AM +0200, Jan Hubicka wrote:
>> I see, the previous implementation tricked the one-declaration rule by
>> introducing two names. What made the difference is that the second name
>> is expanded as builtin...
>>
>> So you don't have __bulitin_
Dear Group ,
We are re-targeting the GCC to the CISC target ,which has the eight
8-bit registers and same register set can used as pair register for
16 bit computation i.e four 16-bits .
Any one in the group tell me ,How do i model this requirement using
the target macros like
REG_CLASS_NA
On Wed, Oct 09, 2013 at 10:59:35AM +0200, Jan Hubicka wrote:
> I see, the previous implementation tricked the one-declaration rule by
> introducing two names. What made the difference is that the second name
> is expanded as builtin...
>
> So you don't have __bulitin_sync_synchronize() at hand th
> On Oct 9, 2013, at 2:14 AM, Umesh Kalappa wrote:
>
> Dear Group,
>
> The below asm is generated for target cortex-m3 (gcc-4.6.3)
>
> main:
>@ args = 0, pretend = 0, frame = 0
>@ frame_needed = 0, uses_anonymous_args = 0
>push {r3, r4, r5, lr}
>bl vAlgTNoOptimize
>movs
Dear Group,
The below asm is generated for target cortex-m3 (gcc-4.6.3)
main:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
push {r3, r4, r5, lr}
bl vAlgTNoOptimize
movs r0, #170
bl vFnCall
bl vAlgTOptimize
ldr r4, .L22
add
> Jan Hubicka writes:
> >> MIPS16 code can't do atomic operations directly, so it calls into
> >> out-of-line
> >> versions that are compiled as -mno-mips16. These out-of-line versions use
> >> the same open-coded implementation as you'd get in normal -mno-mips16 code.
> >
> > Hmm, and I assume
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