HI:
found mult-acc insns like madd.s/d are only used when -mfp64 is specified,
as to codes, there macros defined as:
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| (ISA_MIPS32R2 && TARGET_FLOAT64) \
<--only float 64
Snapshot gcc-4.4-20100720 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.4-20100720/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.4 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
Am 20.07.2010 19:24, schrieb Jonathan Wakely:
> On 20 July 2010 01:36, Martin Gieseking wrote:
>> Does anybody know if this is a known issue, or should I file a bug report?
>
> Please file a bug report, if it's a known issue someone will mark it
> as a duplicate.
Done (http://gcc.gnu.org/bugzilla
On 20 July 2010 01:36, Martin Gieseking wrote:
> Does anybody know if this is a known issue, or should I file a bug report?
Please file a bug report, if it's a known issue someone will mark it
as a duplicate.
Hi,
after tracking down an issue [1] in dvisvgm [2] related to GCC 4.5.0, it
turned out that GCC 4.5.0 doesn't handle sub-classes defined and
instantiated in a template's method properly. At least on x86_64 Linux
systems, the code listed below leads to a segfault, while it works on
Windows/MinGW (
Chris Wulff wrote:
I'm trying to track down a bug in the -fPIC support for microblaze.
I'm currently using the gcc 4.1.2 tree from the Xilinx git repository
but the microblaze 4.5 branch from svn shows the same symptom.
It appears that what is going on is that it is creating a non-PIC
symbol
redriver jiang writes:
> I am porting GCC to a 8bit architecture, and now I have problem on
> reload problem on addressing mode.
> Besides 15 general registers, it has three 16bit address registers,
> R16,R17,R18.
> R16,R17,R18 are able to be as base register in "base" address mode,
> but only R1
Hi,
I am porting GCC to a 8bit architecture, and now I have problem on
reload problem on addressing mode.
Besides 15 general registers, it has three 16bit address registers,
R16,R17,R18.
R16,R17,R18 are able to be as base register in "base" address mode,
but only R18 can be base regs for "base+off
Joern Rennecke wrote:
> I've found two bugs in truncdfsf2;
> I've also added back a number of hunks that Naveen had dropped.
>
> Note that most of the patch has been prepared in 2006, so that is the
> proper most recent copyright date for those files that haven't been touched
> save for swapping
Mikael Pettersson writes:
> The prototypes for two ARM EH routines don't match their actual
> definitions in eh_arm.cc, resulting in build-time warnings. When
> -Werror is active, the build fails. See PR44902.
>
> Fixed simply by updating the prototypes to match the definitions.
>
> Test
The prototypes for two ARM EH routines don't match their actual
definitions in eh_arm.cc, resulting in build-time warnings. When
-Werror is active, the build fails. See PR44902.
Fixed simply by updating the prototypes to match the definitions.
Tested with crosses to arm-eabi and arm-linux-gnuea
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