Re: irunning, width in bits.

2000-06-26 Thread Garrett Wollman
< said: > I guess that the perfect solution is to be able to hardwire the PCI irqs > in some way once FreeBSD is doing the PnP resource allocation. On typical non-SMP motherboards, the PCI IRQs are hard-wired on the motherboard. That is to say, INTA of slot 13 is wire-OR'd with INTB of slot 14,

Re: irunning, width in bits.

2000-06-26 Thread Nick Hibma
> > >From what I understood from dfr, when switching away from an interrupt > > handler it is converted into a full thread. When the second piece of > > hardware fires an interrupt it could then run at the same time. > > I thought of this almost immediately - it's a bad idea though because it >

Re: irunning, width in bits.

2000-06-26 Thread Mike Smith
> > What about shared interrupts? How are they going to be treated? With the > spl leaving the arena it somehow looks feasible to run one interrupt > source on two different threads if there are two pieces of hardware > attached to the same interrupt line. > > >From what I understood from dfr, w

Re: irunning, width in bits.

2000-06-21 Thread Matthew Dillon
(Moving this to freebsd-smp, Bcc'ing current) :What about shared interrupts? How are they going to be treated? With the :spl leaving the arena it somehow looks feasible to run one interrupt :source on two different threads if there are two pieces of hardware :attached to the same interrupt li

irunning, width in bits.

2000-06-21 Thread Nick Hibma
What about shared interrupts? How are they going to be treated? With the spl leaving the arena it somehow looks feasible to run one interrupt source on two different threads if there are two pieces of hardware attached to the same interrupt line. >From what I understood from dfr, when switching