Re: [src] cvs commit: src/sys/vm vm_zeroidle.c

2002-07-09 Thread Matthew Dillon
: : critical_enter(); < :*CMAP2 = PG_V | PG_RW | phys | PG_A | PG_M;< :invltlb_1pg((vm_offset_t)CADDR2); < : curthread->td_lazytlb = PCPU_GET(cpumask); < : critical_exit(

Re: [src] cvs commit: src/sys/vm vm_zeroidle.c

2002-07-09 Thread Matthew Dillon
I have an idea in regards to the page-zero issue. Presumably we want to avoid doing an IPI to every cpu to clear the TLB, so what we do instead is create a lazy TLB clearing mechanism based on the thread. The scheduler detects the request when it switches the thread in and inv