Running a host with several jails on recent CURRENT (12.0-CURRENT #8 r315187:
Sun Mar 12 11:22:38 CET 2017 amd64) makes me trouble on a daily basis.
The box is an older two-socket Fujitsu server equipted with two four-core
Intel(R) Xeon(R) CPU L5420 @ 2.50GHz.
The box has several jails, each jai
A single Byte access to a 4K Byte aligned region between
the fork and wait/sleep/swap-out prevents that specific
4K Byte region from having the (bad) zeros.
Sounds like a page sized unit of behavior to me.
Details follow.
On 2017-Mar-14, at 3:28 PM, Mark Millard wrote:
> [test_check() between
On 2017-Mar-14, at 4:44 PM, Bernd Walter wrote:
> On Tue, Mar 14, 2017 at 03:28:53PM -0700, Mark Millard wrote:
>> [test_check() between the fork and the wait/sleep prevents the
>> failure from occurring. Even a small access to the memory at
>> that stage prevents the failure. Details follow.]
>
On Tue, Mar 14, 2017 at 03:28:53PM -0700, Mark Millard wrote:
> [test_check() between the fork and the wait/sleep prevents the
> failure from occurring. Even a small access to the memory at
> that stage prevents the failure. Details follow.]
Maybe a stupid question, since you might have written it
[test_check() between the fork and the wait/sleep prevents the
failure from occurring. Even a small access to the memory at
that stage prevents the failure. Details follow.]
On 2017-Mar-14, at 11:07 AM, Mark Millard wrote:
> [This is just a correction to the subject-line text to say arm64
> inst
[This is just a correction to the subject-line text to say arm64
instead of amd64.]
On 2017-Mar-14, at 12:58 AM, Mark Millard wrote:
[Another correction I'm afraid --about alternative program variations
this time.]
On 2017-Mar-13, at 11:52 PM, Mark Millard wrote:
> I'm still at a loss about h
On 03/14/2017 01:37, Mu Lichao wrote:
Hi,
I am trying to enable Intel 82599 10GbE SR-IOV VFs on FreeBSD 12-CURRENT, and
after enabled, the SR-IOV VFs can be seen by pciconf(1), but can not be seen by
lspci(1), which is installed from ports/sysutils/pciutils:
# pciconf -l | tail -2
ixv0@pci0:1:
[Another correction I'm afraid --about alternative program variations
this time.]
On 2017-Mar-13, at 11:52 PM, Mark Millard wrote:
> I'm still at a loss about how to figure out what stages are messed
> up. (Memory coherency? Some memory not swapped out? Bad data swapped
> out? Wrong data swapped
I'm still at a loss about how to figure out what stages are messed
up. (Memory coherency? Some memory not swapped out? Bad data swapped
out? Wrong data swapped in?)
But at least I've found a much smaller/simpler example to demonstrate
some problem with in my Pine64+_ 2GB context.
The Pine64+ 2GB
On 2017-Mar-13, at 11:52 PM, Mark Millard wrote:
> I'm still at a loss about how to figure out what stages are messed
> up. (Memory coherency? Some memory not swapped out? Bad data swapped
> out? Wrong data swapped in?)
>
> But at least I've found a much smaller/simpler example to demonstrate
>
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