Hi Richard,
Am 08.01.2023 um 14:31 schrieb Paul Richard Thomas via Fortran
:
Hi Thomas,
Following your off-line explanation that the seemingly empty looking
assembly line forces an effective reload from memory, all is now clear.
It’s not a full fix (for register vars) and it’s ‚superior‘ t
> Am 08.01.2023 um 14:31 schrieb Paul Richard Thomas via Fortran
> :
>
> Hi Thomas,
>
> Following your off-line explanation that the seemingly empty looking
> assembly line forces an effective reload from memory, all is now clear.
It’s not a full fix (for register vars) and it’s ‚superior‘
Hi Thomas,
I was thinking of a function in resolve.cc, similar
to generate_component_assignments that would generate the final call and,
where necessary, generate a temporary and place rhs finalization after the
assignment. Since this would only involve ordinary assignment and
subroutine calls, I
Hi Thomas,
Following your off-line explanation that the seemingly empty looking
assembly line forces an effective reload from memory, all is now clear.
OK for mainline and for backporting as you see fit.
Thanks for the patch.
Paul
On Sat, 7 Jan 2023 at 15:46, Thomas Koenig via Fortran
wrote:
Hi Paul,
What causes the ICES?
There were a few PRs along this line. Usually, it is the
front-end pass inserting code which is illegal Fortran, and
the later stages then asserting that it doesn't happen.
Here are a few examples:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50690 (function
e
