[PATCH] RISC-V: Add untested 32-bit core file support.

This conflicts with the previoues two patches. Adds 32-bit support exactly the same way that the sparc backend handles 32- and 64-bit core file support. The 64-bit core file support was tested and still works same as before. Signed-off-by: Jim Wilson --- backends/ChangeLog | 11 ++

[PATCH] RISC-V: Add initial return value location support.

Started with the aarch64 support and modified it for RISC-V. The flattened structure support hasn't been written yet, but the rest of it should be correct for the LP64D ABI. We have potentially 6 different ABIs to support, so this requires checking elf header flags in riscv_init when setting the

[PATCH] RISC-V: Improve riscv64 core file support.

This fixes two problems. The offset for x1 is changed from 1 to 8 because this is a byte offset not a register skip count. Support for reading the PC value is added. This requires changing the testsuite to match the new readelf output for coredumps. Signed-off-by: Jim Wilson --- backends/Chan