Re: [Dwarf-discuss] Multiple inlined subroutines for a VLIW instruction bundle?

2024-10-17 Thread John DelSignore via Dwarf-discuss
Hi, I think the best way to encode the information depends on details of the processor architecture. The IA-64 (Intel Itanium architecture) had a VLIW instruction encoding with a 128-bit instruction bundle consisting of three 41-bit instruction slots per bundle plus a 5-bit template indicating

[Dwarf-discuss] Multiple inlined subroutines for a VLIW instruction bundle?

2024-10-17 Thread David Stenberg via Dwarf-discuss
Hi! Is it possible to encode different backtrace information, including inlining, for two different instructions in a VLIW bundle? I'll probably use inprecise and non-standard wording below. Sorry if that is the case. Assume that the following C program: foo.h: static inline void foo_inl_in