Hi,
In the FDE one could, in theory, emit a DW_CFA_def_cfa_expression for the ADDNE
and BEQ along the lines of (modulo bugs):
ULEB128
;Extract the mode bits from the CPSR (or wherever your processor stores
condition flags)
DW_OP_bregx CPSR, 0 ; If the CPSR isn't numbered (e.g. in ARM D
Anyone have any suggestions for Jonathan?
On 04/22/2013 11:47 AM, Humphreys, Jonathan wrote:
Sure, I'll use ARM as it's a pretty well-known processor.
Suppose I have an epilog that consists of stack deallocation and a combined SOE
register save and return. And suppose that the predecessor blo
