--
Sir/Madam,
I have access to very vital information that can be used to move a huge
amount of money. I have done my homework very well and I have the
machineries in place to get it done since I am still in active service.
If it was possible for me to do it alone I would not have bothered
ig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a005-20201030
x86_64 randconfig-a001-20201030
x86_64 randconfig-a002-20201030
x86_64
defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a005-20201030
x86_64
Hi Paul,
On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> Both 10 and 12-bit Bayer formats are stored aligned as 16-bit values
> in memory, not unaligned 10 or 12 bits.
>
> Since the current code for retreiving the bpp is used only to
> calculate the memory storage size of the picture (which is wh
Hi Paul,
On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on the other. I
Hello,
On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> is already supported and used for MIPI DSI this adds support for the
> former, to be used with MIPI CSI-2.
>
> This implementation is inspired by the Allwinner BSP impl
Hi Paul,
I have some comments through the series, I hope this helps.
On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> This series introduces support for MIPI CSI-2, with the A31 controller that is
> found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
> controller. While the
Hi Paul,
On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> As some D-PHY controllers support both Rx and Tx mode, we need a way for
> users to explicitly request one or the other. For instance, Rx mode can
> be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
>
> Introduce new MI
On 10/29/2020 2:52 PM, Brian O'Keefe wrote:
Add 024c:0627 to the list of SDIO device-ids, based on hardware found in
the wild. This hardware exists on at least some Acer SW1-011 tablets.
Signed-off-by: Brian O'Keefe
---
drivers/staging/rtl8723bs/os_dep/sdio_intf.c | 1 +
1 file changed, 1 in
Hi Paul,
On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++
> 1 file changed, 1
On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++
> 1 file changed, 168 inserti
On Fri, 30 Oct 2020 13:22:31 +0100 gregkh wrote:
> On Thu, Oct 29, 2020 at 10:06:14PM +0100, Arnd Bergmann wrote:
> > The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
> >
> > Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)
> >
> > are available in the Git repository at:
>
Hi!
On Fri, Oct 30, 2020 at 12:06:10PM +0100, Hans Verkuil wrote:
> Maxime,
>
> Are you OK with this series? It looks good to me.
I am, you can take it. I'll merge the dt patches through arm-soc
Thanks!
Maxime
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On Thu, 22 Oct 2020 17:58:55 +0200, Nicolas Saenz Julienne wrote:
> The PWM bus controlling the fan in RPi's official PoE hat can only be
> controlled by the board's co-processor.
>
> Signed-off-by: Nicolas Saenz Julienne
>
> ---
> Changes since v1:
> - Update bindings to use 2 #pwm-cells
>
>
On Thu, Oct 29, 2020 at 10:06:14PM +0100, Arnd Bergmann wrote:
> The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
>
> Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org:/pub/scm/linux/kernel/git/arnd/pla
Maxime,
Are you OK with this series? It looks good to me.
Regards,
Hans
On 12/09/2020 16:30, Martin Cerveny wrote:
> First patch extends cedrus capability to all decoders
> because V3s missing MPEG2 decoder.
>
> Next two patches add system control node (SRAM C1) and
> next three patch
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