On Fri, 3 Jun 2022 at 04:00, Jessica Zhang wrote:
>
>
>
> On 6/2/2022 3:31 PM, Dmitry Baryshkov wrote:
> > On 27/05/2022 23:11, Jessica Zhang wrote:
> >>
> >>
> >> On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
> >>> On 27/05/2022 21:54, Jessica Zhang wrote:
> Add support for setting MISR reg
On 6/2/2022 3:31 PM, Dmitry Baryshkov wrote:
On 27/05/2022 23:11, Jessica Zhang wrote:
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/
On 27/05/2022 23:11, Jessica Zhang wrote:
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_
On 2022-05-27 22:38:24, Dmitry Baryshkov wrote:
> [..]
> > #define INTF_CFG2_DATABUS_WIDEN BIT(0)
> > #define INTF_CFG2_DATA_HCTL_ENBIT(4)
> >
> > +#define INTF_MISR_CTRL 0x180
> > +#define INTF_MISR_SIGNATURE0x184
> > +#define INTF_MISR_FRAME_COUNT_
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
