[PATCH v1] tests: Add test suite for double-checking userptr write validity and VRAM

Userptr resides in host memory, and PCIe writes involve cache coherence. By using SDMA to copy GTT to VRAM and then verifying the values in VRAM, we can validate GTT cache coherence. Bo(Userptr) > SDMA ---> Bo(userptr) sdma-> VRAM Signed-off-by: zhangzhijie --- tes

Re: [PATCH v1] Support Intel Xe GPU dirver Porting on RISC-V Architecture

robe to '*' (or the particular GPU ID) is required, but otherwise stability is good. For example, the A750: https://github.com/geerlingguy/raspberry-pi-pcie-devices/issues/510#issuecomment-3383284831 On Jul 15, 2025, at 1:18 AM, zhangzhijie wrote: inb/outb speccial wire not supp

[PATCH v1] drm/xe: Support Intel Xe GPU dirver Porting on RISC-V Architecture

inb/outb speccial wire not support on other ARCH. Should detect whether arch platform support or not. Signed-off-by: zhangzhijie --- drivers/gpu/drm/i915/display/intel_vga.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm

[PATCH v1] Support Intel Xe GPU dirver Porting on RISC-V Architecture

inb/outb speccial wire not support on other ARCH. Should detect whether arch platform support or not. Signed-off-by: zhangzhijie --- drivers/gpu/drm/i915/display/intel_vga.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm